This invention relates to memory interface circuits for integrated circuits such as programmable logic device integrated circuits, and more particularly, to memory interface circuits with phase detectors and delay-locked loops for adjusting clock signals.
Programmable logic devices are a type of integrated circuit that can be programmed by a user to implement a desired custom logic function. In a typical scenario, a logic designer uses computer-aided design tools to design a custom logic circuit. When the design process is complete, the tools generate configuration data. The configuration data is loaded into a programmable logic device to configure the device to perform the functions of the custom logic circuit.
In a typical system, a programmable logic device integrated circuit is mounted on a circuit board with memory chips and other integrated circuits. When performing write and read operations on a memory, timing is critical. Because programmable logic devices are configured in many different ways and are installed on many different types of boards, the lengths of the traces that interconnect the programmable logic device and the memory can vary from one system to another. As a result, it is not generally possible to know in advance exactly how the data and clock paths between a programmable logic device and a memory will perform. In some systems the data and clock paths may have one set of timing characteristics, whereas in other systems the data and clock paths may have a different set of timing characteristics.
To accommodate variations in timing performance due to different systems environments, conventional programmable logic devices use numerous variable delay chain circuits to process the data and clock signals that are generated by a memory. While this approach can be satisfactory in many instances, using many variable delay chain circuits in a programmable logic device tends to consume relatively large amounts of circuit resources.
It would be desirable to be able to provide integrated circuits such as programmable logic device integrated circuits with memory interface circuitry that makes efficient use of on-chip resources.